Samsung reveals 16-layer 3D DRAM plans with VCT DRAM as a stepping stone — IMW 2024 details the future of compact, higher density RAM

Samsung
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Samsung is pushing hard to develop 3D DRAM, the future of compact RAM, according to its presentation at IMW 2024. VCT (vertical channel transistor) DRAM is the first mountain to climb in this goal, and Samsung is scheduled to complete initial development on it next year, with 3D DRAM seeing commercialization by 2030.

IMW 2024, an international conference for computer memory vendors, is where Samsung most recently outlined its developments in the field of DRAM innovation per ZDNet Korea. Lee Si-woo, Vice President of Samsung, spoke on Samsung's research in 4F Square VCT DRAM and 3D DRAM.

"Industrial developments such as hyperscaler AI and on-demand AI require a lot of memory processing ability. On the other hand, the microprocessing technology of existing DRAM is limited," said Lee. But in the coming years, Lee predicts "new innovations are expected to occur in the structure of cells."

One such innovation is the arrival of 4F Square VCT DRAM, the most compact DRAM design yet. The 4F Square design will utilize vertical stacking to reduce DRAM cell sizes by around 30% from today's standard 6F Square DRAM cell structure. 4F Square, in addition to being more horizontally compact, would become more power-efficient than its predecessors, but requires extreme precision in fabrication, better materials for production, and further research to make it scalable and mass-producible. Very few companies even claim to have made the tech work so far.

"Many companies are making efforts to transition to 4F Square VCT DRAM," said Vice President Lee. "However, for this to happen, the development of new materials such as oxide channel materials and ferroelectrics must take precedence." Samsung's 4F Square process will see an internal release in 2025, as announced at IMW 2024.

Vertical DRAM stacking, like 4F Square and eventually truly 3D DRAM, are the next steps for innovation in capacity increase and efficiency in DRAM. The industry has been aiming in this direction for over a decade, but has been especially spurred on by the commercial and functional success of 3D NAND, a similar principle applied to NAND Flash memory. 3D NAND, first introduced to the market by Samsung in 2013 (Samsung calls it V-NAND) will be the inspiration for 3D DRAM, with a major wrinkle.

NAND flash is a passively powered technology, so it can save data while powered off, like how a cell phone stores files even when turned off. This non-volatile memory is quite different from DRAM, a volatile memory that can only save data while it has power. DRAM's volatile nature makes it considerably faster and much more reliable than NAND, but it also makes stacking DRAM layers considerably harder than stacking NAND, as more power and data must be able to go up and down the stacked layers.

This considerable challenge in engineering plus Samsung's belief that 3D DRAM will demand the adoption of new materials for capacitors and bitlines means that Samsung does not plan to have 3D DRAM commercially available until 2030. Samsung likely won't be defeated in this race, as their internal predictions are ahead of industry expectations. Tokyo Electron predicts that even VCT DRAM will not see commercial release until 2027.

But Samsung have been known to buck trends in memory expectations before. 3D NAND was thought to have a theoretical ceiling of 128 stacked layers but Samsung stands ready to release 290-layer products this year.

Freelance News Writer
  • Metal Messiah.
    Vertical DRAM stacking, like 4F Square and eventually truly 3D DRAM, are the next steps for innovation in capacity increase and efficiency in DRAM.

    It would be much better if they refer any 3D DRAM as vertically stacked cell array transistors (VS-CAT) instead. Because that's what the tech is all about.

    YMTC’s Xstacking technology shares a very similar concept. And VS-CAT, unlike existing DRAMs, combines two silicon wafers. The peripheral, or logic, and memory cells are all attached individually.

    Sometimes it gets confusing to others whether it is actual die-stacking or cell stacking.

    Because in the case 3D DRAM, attaching the peripheral next to the cell layer like existing DRAMs will cause it to have a large surface area. Hence to avoid this, the peripheral is made on another wafer to the memory cells and attached through bonding.

    BTW, Samsung also mentioned the usage of backside power delivery network (BSPDN) technology to 3D DRAM.
    Reply
  • TechyIT223
    Seems like a very early concept for that much capacity of dram. Not to mention the high production price of manufacturing.

    One would think 2027 would be a timeline for this tech but I doubt it's a bit of speculation at this point. 🧐
    Reply
  • Metal Messiah.
    They are just laying the groundwork for now. Innovation takes time. 3D DRAM development is still in its infancy.

    There are difficulties which include expensive starting expenses and intricate production procedures.
    Reply
  • TechyIT223
    Makes sense
    Reply